Implementation of Multi-standard Wireless Communication Receivers in a Heterogeneous Reconfigurable System-on-Chip

Future mobile terminals become multi-mode communication systems. In order to handle different standards, we propose to perform baseband processing in heterogeneous reconfigurable hardware. Not only the baseband processing but also error decoding differs for every communication system. We already proposed implementations of the baseband processing part of an OFDM receiver and a Wideband CDMA receiver in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. Now, we also implemented an adaptive Viterbi decoder in the same coarse-grained MONTIUM architecture. The rate, constraint length and decision depth of the decoder can be adjusted to different communication systems. We show that the flexibility in the coarse-grained reconfigurable architecture is more than 200 times as energy-efficient compared to a general purpose solution but only 24 times less efficient compared to a dedicated solution

Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture

Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture

Overview of the tool-flow for the Montium Processing Tile

This paper presents an overview of a tool chain to support a transformational design methodology. The tool can be used to compile code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Data Flow Graph (CDFG). A Control Dataflow Graph contains not only the dataflow operations (e.g. arithmetic or logical operations on data) but also control flow operations (e.g. operators for loop and if then else constructs). The CDFG is minimized using a set of behavior preserving transformations such as dependency analysis, common sub-expression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture

Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture

Mobile wireless communication systems become multi-mode systems. These future mobile systems employ multiple wireless communication standards, which are different by means of algorithms that are used to implement the baseband processing and the channel decoding. Efficient implementation of multiple wireless standards in mobile terminals requires energy-efficient and flexible hardware. We propose to implement both the baseband processing and channel decoding in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains many processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. We already showed the feasibility to implement the baseband processing of OFDM and WCDMA based communication systems in the MONTIUM. In this paper we implemented two kinds of channel decoders in the same MONTIUM architecture: Viterbi and Turbo decoding

Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture

Summary form only given. A heterogeneous system-on-chip (SoC) architecture for mobile hand-held devices is proposed to overcome the battery bottleneck in these devices. This SoC contains processing tiles of different granularities. The Montium coarse-grain reconfigurable tile processor is presented. Also, an introduction to HiperLAN/2 baseband processing is given. The implementation of a HiperLAN/2 receiver on the Montium reconfigurable architecture is explained in detail. The hardware of this implemented receiver has been simulated and the performance figures are given. The configuration overhead for the receiver is very small, which enables dynamic reconfiguration. The required computational performance can be obtained at very low clock frequencies. The Montium coarse-grain reconfigurable architecture enables an energy and area efficient implementation of a HiperLAN/2 receiver